MC74HC4060AD |
RFQ for MC74HC4060AD Required Field |
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| Technical/Catalog Information | MC74HC4060ADG |
| Vendor | ON Semiconductor |
| Category | Integrated Circuits (ICs) |
| Logic Type | Binary Counter |
| Trigger Type | Negative Edge |
| Voltage - Supply | 2 V ~ 6 V |
| Number of Bits per Element | 14 |
| Number of Elements | 1 - Single |
| Direction | Up |
| Mounting Type | Surface Mount |
| Package / Case | 16-SOIC |
| Reset | Asynchronous |
| Packaging | Tube |
| Operating Temperature | -55°C ~ 125°C |
| Count Rate | 50MHz |
| Timing | - |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | MC74HC4060ADG MC74HC4060ADG MC74HC4060ADGOS ND MC74HC4060ADGOSND MC74HC4060ADGOS |
| Product | Manufacturers | Pack | D/C |
| MC74HC4060AD | - | 04+ | SOP3.9 |
The MC74C4060A is identical in pinout to the standard CMOS MC14060B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This device consists of 14 masterslave flipflops and an oscillator with a frequency that is controlled either by a crystal or by an RC circuit connected externally. The output of each flipflop feeds the next and the frequency at each output is half of that of the preceding one. The state of the counter advances on the negativegoing edge of the Osc In. The activehigh Reset is asynchronous and disables the oscillator to allow very low power consumption during standby operation.
State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with Osc Out 2 of the HC4060A.
Features |
| • Output Drive Capability: 10 LSTTL Loads• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2 to 6 V• Low Input Current: 1 mA• High Noise Immunity Characteristic of CMOS Devices• In Compliance With JEDEC Standard No. 7A Requirements• Chip Complexity: 390 FETs or 97.5 Equivalent Gates |
| Symbol | Parameter | Value | Unit |
| vcc | DC Supply Voltage (Referenced to GND) | 0.5 to +7.0 | V |
| VIN | DC Input Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| VOUT | DC Output Voltage (Referenced to GND) | 0.5 to VCC + 0.5 | V |
| LIN | DC Input Current, per Pin | ±20 | mA |
| IOUT | DC Onput Current, per Pin | ±25 | mA |
| ICC | DC Supply Current Per Supply Pin | ±50 | mA |
| PD | Power dissipation in still air piastic DIP SOIC package |
750 500 450 |
mW |
| TSTG | Storage Temperature | 65 to +150 | °C |
| TL | Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) |
260 |
°C |
